Optimal operating temperature for industry-compatible silicon spin quantum computing: colder is not necessarily better

Source: arXiv:2607.11846 · Published 2026-07-13 · By Paul Steinacker, Amanda E. Seedhouse, Nard Dumoulin Stuyck, Tuomo Tanttu, MengKe Feng, Santiago Serrano et al.

TL;DR

This paper addresses the critical and practical challenge of determining the optimal operating temperature for silicon spin qubits in large-scale fault-tolerant quantum computers compatible with industrial semiconductor fabrication. While millikelvin temperatures offer the highest gate fidelities, scaling to millions of qubits poses severe refrigeration power constraints due to limited cooling capacity and Carnot efficiency. The authors experimentally benchmark temperature-dependent qubit performance via gate set tomography (GST) on both industrial (imec 300 mm wafer) and academic silicon spin qubits over a temperature range from ~20 mK to ~1.5 K. They observe consistent power-law degradation of coherence times and gate/state-preparation-measurement fidelities, with a crossover temperature near 0.5–1 K where errors increase sharply. Using these measured fidelities, they develop a comprehensive system-level power model that incorporates competing trade-offs between refrigeration power and error-correction overhead, showing that the total power consumption of a silicon quantum computer has a distinct minimum at a finite temperature around 0.5–1.5 K. This challenges the intuitive notion "colder is always better" and connects low-level physics to architectural design. The experimental and modeling results thus provide guidance for choosing silicon qubit operating temperatures that optimize quantum computing performance and energy efficiency simultaneously.

Key findings

• Gate and SPAM infidelities of silicon spin qubits increase with temperature following a power-law form M = κ(1 + (T/TX)^n), with crossover temperatures TX spanning 0.3–1.14 K and exponents n in the range 2–5 across devices.
• Relaxation time T1 and coherence times T2* and T2,Hahn universally degrade with temperature, with crossover points around 0.3–0.8 K and power-law scaling consistent across both industrial and academic device fabrication processes.
• GST benchmarking reveals two-qubit gate fidelities remain above 99% and single-qubit fidelities above 99.9% up to approximately 0.5–0.7 K, beyond which performance rapidly deteriorates.
• Dephasing errors (Z-type) dominate the fidelity degradation at elevated temperatures, linked to reduced spin coherence and relaxation times.
• A generalized power consumption model combining refrigeration costs, qubit infidelities, and quantum error correction (specifically surface code overhead scaling) predicts a finite optimal operating temperature, typically around 0.5–1.5 K, for minimizing total power use.
• Cooling power increases drastically with decreasing temperature, but higher qubit error rates at warmer temperatures cause larger error-correction resource overhead that increases power consumption quadratically with code distance d.
• Measurements on industry-compatible devices indicate robustness to operation near 1 K, enabling potential integration of cryogenic CMOS control electronics, but fidelity loss above ~1 K remains a bottleneck.
• Optimal temperature results hold qualitatively under parameter variations and different error models, implying a general architectural design principle beyond specific devices.

Threat model

This work does not consider an adversarial threat model but rather the passive impact of thermal noise and temperature-induced decoherence on silicon spin qubit performance and consequent system-level power trade-offs in fault-tolerant quantum computing architectures.

Methodology — deep read

The authors take a detailed empirical and modeling approach to characterize and analyze temperature-dependent silicon spin qubit performance and system power tradeoffs.

1. Threat Model & Assumptions: The focus is on thermal effects and fidelity degradation impacting quantum error correction and total power consumption for fault-tolerant quantum computing. The adversary is indirect—thermal noise limiting gate fidelity—rather than an active attacker. Assumptions include fixed target logical error rates, a surface code error correction scheme with known overhead models (α=0.3, β=70), and qubit error rates equated across gate types for simplification.

2. Data: Six two-qubit devices are tested— three industrially fabricated at imec on 300 mm wafers (devices A–C), three academically fabricated (D–F). Devices used isotopically enriched Si with residual 29Si between 50 and 800 ppm. Spin qubits are formed in double quantum dots operating at charge configurations like (1,3) or (3,3). Electron temperatures are measured indirectly via charge transition broadening. Device performance is benchmarked over 20 mK–1.5 K without re-optimization at higher temperatures.

3. Architecture/Algorithm: Gate set tomography (GST) is applied to quantify single- and two-qubit gate fidelity, state preparation and measurement (SPAM) errors, decomposed into stochastic and coherent components. Gate sets include {I, X, Z, CZ} and DCZ with gate times ranging from ~200 to 4000 ns depending on device. The fidelity temperature dependence is modeled as a power-law with parameters κ (baseline infidelity), TX (crossover temperature), and n (exponent).

4. Training Regime: Not applicable as this is experimental characterization rather than ML training.

5. Evaluation Protocol: Fidelity metrics (gate infidelities, SPAM infidelities, T1, T2 times) are measured repeatedly at multiple temperatures, with 95% confidence intervals reported. Power-law fits are performed to characterize temperature dependence. The system-level power model incorporates measured fidelities to estimate overhead from the rotated surface code, calculating required physical qubits and consequent cooling power from generalized Carnot refrigeration efficiency (η = 0.25) across temperatures. Trade-offs between cooling and error correction are evaluated for fixed logical qubits (500) and logical error rate targets.

6. Reproducibility: Code and detailed operational parameters are not explicitly released. Device fabrication details are given, and methods from prior works referenced. Electrical characterization and tomography protocols rely on established standards. Extended data supports model variants and parameter sensitivity.

Concrete Example End-to-End: Device E (academic with 50 ppm 29Si) shows κ=0.0012, TX=1.14 K, n=3.41 for gate infidelity. At 0.5 K, gate fidelity ~99%, cooling power is manageable. At 1.5 K, infidelity increases, requiring higher code distance d to maintain logical error rates, leading to more physical qubits and higher total power, offsetting cooling savings. The resulting total system power exhibits a minimum near 1 K, illustrating the tradeoff quantitatively.

Technical innovations

• Experimental identification and quantification of a common temperature crossover (TX ~0.5–1 K) in gate fidelity degradation across both industrial and academic silicon spin qubits.
• Use of gate set tomography (GST) to decompose two-qubit silicon gate errors into stochastic and Hamiltonian components and track their temperature dependence in detail.
• Development of a holistic system-level power consumption model linking measured qubit temperature-dependent infidelities to error correction overhead and cryogenic refrigeration energy as competing contributions.
• Demonstration that the trade-off between refrigeration efficiency and quantum error correction overhead yields a finite optimum operating temperature for silicon spin qubit processors, challenging the assumption that colder always means better.

Datasets

• Devices A–C (industrial): 3 two-qubit silicon spin qubits, imec 300 mm wafer fabrication
• Devices D–F (academic): 3 two-qubit silicon spin qubits, fabricated at Australian National Fabrication Facility
• Device E specific: fabricated with 50 ppm residual 29Si isotopic enrichment

Baselines vs proposed

• Device A baseline SPAM fidelity > 99.9%, two-qubit gate fidelity > 99% at 20 mK versus fidelity deteriorating above 0.5 K
• GST measured gate infidelities remain < 1% up to ~0.5–0.7 K across devices A–D, rising quickly beyond that
• Power model baseline cooling power rises by 5 orders of magnitude from 1 K to 20 mK for fixed electrical input power
• Total power consumption for fixed logical qubit count minimized near 0.5–1.5 K compared to both millikelvin and ~1.5 K operation

Figures from the paper

Figures are reproduced from the source paper for academic discussion. Original copyright: the paper authors. See arXiv:2607.11846.

Fig 1: | Fidelity and operating power as a function

Fig 2: | Relaxation and coherence time. a, Relaxation time, T1, of devices A–C and E as a function of temperature

Fig 6: | Power consumption as a function of

Fig 4 (page 15).

Fig 5 (page 16).

Limitations

• Fidelity measurements performed on a limited number of two-qubit devices; scalability to larger qubit arrays could reveal additional variations.
• No direct adversarial or fault-injection tests to stress error correction resilience at elevated temperatures.
• Theoretical model assumes uniform physical error rates across gates, simplifying real-world heterogeneity.
• Classical control power consumption excluded from total system power modeling, possibly underestimating thermal budget impact of electronics.
• The power model assumes a generalized Carnot refrigerator with fixed relative efficiency η=0.25; specific cryocoolers might differ in performance.
• Potential device-to-device variability and environmental noise not fully characterized in dataset.

Open questions / follow-ons

• What are the dominant microscopic physical mechanisms causing the fidelity degradation near the crossover temperature in silicon spin qubits, and how can materials or device engineering address them?
• How does the presence of integrated classical control electronics at cryogenic stages affect overall power and optimal operating temperature?
• Can advanced dynamic decoupling or driven gate schemes extend high-fidelity operation well above 1 K to shift or eliminate the crossover?
• How do larger, multi-qubit silicon quantum processors behave in terms of temperature-dependent fidelity and total system power when scaled beyond the two-qubit devices studied here?

Why it matters for bot defense

For bot-defense and CAPTCHA practitioners interested in system-level security implications of silicon spin quantum computing technologies, this paper highlights that optimal operating parameters for quantum processors require carefully balancing device physics and operational overheads rather than simply maximizing qubit coherence by lowering temperature. Applied to security contexts, understanding such hardware-level operational constraints is crucial when evaluating quantum threat models or assessing quantum resources for cryptanalysis. The findings show that even future large-scale silicon spin quantum computers face fundamental engineering trade-offs influencing their realistic deployment and power consumption. This informs realistic threat timelines and can shape defensive strategies accordingly, especially in cryptographic tasks potentially vulnerable to quantum attacks. However, no direct bot-defense or CAPTCHA techniques arise; the paper's value lies in grounding expectations about practical quantum computing capability evolution.

Cite

@article{arxiv2607_11846,
  title={ Optimal operating temperature for industry-compatible silicon spin quantum computing: colder is not necessarily better },
  author={ Paul Steinacker and Amanda E. Seedhouse and Nard Dumoulin Stuyck and Tuomo Tanttu and MengKe Feng and Santiago Serrano and Ensar Vahapoglu and Samuel K. Bartee and Philip Y. Mai and Alexis Shaw and Andreas Nickl and Sebastian Pauka and Brendan Harlech-Jones and Juan P. Dehollain and Fay E. Hudson and Kok Wai Chan and Thomas A. Ohki and David Reilly and Christopher C. Escott and Chih Hwan Yang and Wee Han Lim and Arne Laucht and Andre Saraiva and Andrew S. Dzurak and Jared H. Cole },
  journal={arXiv preprint arXiv:2607.11846},
  year={ 2026 },
  url={https://arxiv.org/abs/2607.11846}
}

Read the full paper

• arXiv:2607.11846 (abstract)
• arXiv:2607.11846 (PDF)