Quantum Software Engineering in Practice: FPGA and AI Integration for Quantum Certification

Source: arXiv:2607.07597 · Published 2026-07-08 · By Marcos Guillermo Lammers, José Manuel Suárez, Adrián Pousa, Luis Mariano Bibbó, Alejandro Fernández

TL;DR

This paper addresses the challenge of systematically certifying quantum computers in the noisy intermediate-scale quantum (NISQ) era through a Quantum Software Engineering (QSE) methodology. It introduces QAccCert, a hybrid certification framework integrating FPGA acceleration and Artificial Intelligence (AI), specifically large language models (LLMs), to optimize measurement parameters for entanglement certification via CHSH inequality violation. The framework abstracts hardware details via modular architecture and validates the approach through quantum simulations using Qiskit AerSimulator. Results show that an LLM-guided search achieves 99.94% of the theoretical CHSH violation limit (2√2), outperforming random and local search strategies, while FPGA acceleration provides a nearly 10x speedup over CPU computations for correlation evaluations. The study demonstrates the practicality and scalability of combining heterogeneous classical technologies with quantum hardware simulations under QSE principles, setting a precedent for future NISQ device certification and hybrid quantum-classical system development.

Key findings

• The LLM optimization achieves a CHSH violation S = 2.8267, corresponding to 99.94% of the theoretical maximum 2√2 ≈ 2.828, outperforming random search (S = 2.7520, 97.3%) and local perturbation fallback (S = 2.7686, 97.9%) in solution quality.
• LLM optimization requires 41 iterations on average to converge, slightly more than the fallback (35 iterations) and random search (42 iterations), indicating better quality but not fewer iterations.
• FPGA hardware acceleration projected with USB 3.0 interface reduces iteration computation time to approximately 0.00084 ms compared to 0.00197 ms on CPU, yielding a 9.4× speedup for processing 4 correlations in parallel.
• Current UART-based FPGA prototype has 554 ms per iteration due to communication delays, but UBS 3.0 interface projection shows potential for real-time scalable throughput.
• Hybrid architecture with modular separation allows hardware abstraction and easy replacement of FPGA or LLM modules without affecting orchestrator logic, enhancing reusability and adaptability.
• LLM-guided optimization leverages prior measurement history effectively, enabling adaptive exploration of parameter space tailored to hardware imperfections rather than blind random sampling.
• Simulation experiments (Qiskit Aer without noise model) validate conceptual feasibility, although real NISQ devices are expected to achieve lower CHSH violations (around 2.3–2.7) due to noise and decoherence.
• FPGA acceleration scales to thousands of correlations in parallel with near-constant computation time, suggesting suitability for future high-demand quantum certification workloads.

Threat model

The adversary is implicitly the physical imperfections, noise, and decoherence inherent in NISQ quantum hardware, which may degrade entanglement quality and invalidate ideal certification assumptions. The system assumes no malicious actor altering measurement results; rather, the challenge is adapting to unpredictable hardware errors and environmental variability. The certification framework cannot directly control quantum hardware faults but must identify when results reflect valid entangled states despite these effects.

Methodology — deep read

1. Threat Model & Assumptions: The adversary scenario is implicit—the certification system must verify the entanglement quality of quantum states produced by inherently noisy and imperfect NISQ hardware. The system assumes limited knowledge of hardware imperfections, which fluctuate (thermal drift, noise, decoherence). The adversary is environmental noise and hardware errors; no malicious adversary is explicitly modeled.

2. Data: Quantum state measurement data is simulated using Qiskit AerSimulator with finite shot counts. The CHSH correlation values E(α,β) are computed for 4 measurement settings using parameterized Bell state circuits. No experimental or noisy data was used; results are from idealized simulations.

3. Architecture / Algorithm: QAccCert is a modular framework consisting of:

   • Quantum State Preparation Module: generates Bell states parametrized by angles θ = [a, a', b, b'] using standardized Qiskit API
   • FPGA-Accelerated Processing Module: receives raw measurement results via UART, computes four E(α,β) correlations in parallel using Verilog code deployed to an open-source iCE40 FPGA hardware platform (Kéfír project). Exposes a simple interface to the orchestrator.
   • AI Optimization Module: uses LLMs (Mistral-7B-Instruct-v0.2 and DistilGPT2) to analyze history of angle-S value pairs, propose new θ values by constructing prompts encoding past iterations, parsing JSON responses,
   • Main Orchestrator: controls data flow, synchronizes modules, handles configuration, convergence criteria, and iteration logic.

4. Training Regime: No ML training described; LLMs are pretrained models used in inference mode to propose parameter updates. The FPGA firmware is synthesized once with Icestudio. Iterative loop runs up to Nmax = 50 iterations or until S is close to theoretical max.

5. Evaluation Protocol: The system compares three optimization strategies: pure random search, fallback local perturbation around best angles, and LLM-guided angle suggestion. Each method runs identical quantum circuits and FPGA computations. Metrics include best S value achieved (violation), number of iterations, time per iteration (CPU vs FPGA), overall execution time. Simulation without noise models isolates algorithmic and hardware performance. Statistical variations (std dev) are noted but not deeply detailed. Baselines include CPU-only correlation computations and random search optimization.

6. Reproducibility: Source code and FPGA designs are publicly available on GitHub. The quantum backend simulation uses Qiskit Aer, a standard open-source framework. LLM models are open-source releases accessible via web APIs. Real NISQ hardware integration is future work.

Concrete example: At iteration i, the system uses current angle vector θcurrent to prepare a Bell state on Qiskit AerSimulator, measures four correlations E(α,β). These raw results are sent to FPGA accelerated module via UART, FPGA computes E(α,β) values rapidly. The orchestrator receives S computed from these correlations. If S > previous best, θbest updated; else either fallback local search or LLM is queried for next θcurrent. LLM receives entire iteration history, constructs prompt, returns suggested angles. Process repeats until convergence or max iterations. The FPGA accelerates the computational bottleneck of correlation calculation while the LLM provides adaptive, memory-based parameter optimization.

Technical innovations

• Integrating FPGAs as low-level accelerators for parallel computation of quantum correlations in the certification process, significantly speeding classical post-processing.
• Using large language models (LLMs) to guide the search for optimal measurement parameters adaptively, leveraging iteration history for more efficient parameter space exploration than random search.
• Designing a modular Quantum Software Engineering (QSE) architecture enabling hardware abstraction, separation of concerns, and reusability in quantum-classical hybrid systems.
• Employing open-source FPGA hardware (Kéfír project) and visual development tools (Icestudio) to democratize quantum hardware acceleration integration.
• Projecting scalable throughput for correlation computations from tens to thousands of operators via FPGA parallelism with negligible time increase.

Baselines vs proposed

• Pure random search: S = 2.7520 (97.3% of theoretical max), iterations = 42 vs LLM optimization (Distil GPT-2): S = 2.8267 (99.94%), iterations = 41
• Fallback local perturbation: S = 2.7686 (97.9%), iterations = 35 (fastest convergence) vs LLM optimization (Mistral-7B): S = 2.6909 (95.1%), iterations = 46
• CPU-only correlation computation time per iteration = 0.00197 ms vs projected FPGA+USB 3.0 time per iteration = 0.00084 ms (9.4× speedup)

Figures from the paper

Figures are reproduced from the source paper for academic discussion. Original copyright: the paper authors. See arXiv:2607.07597.

Fig 1: Hybrid architecture of QAccCert.

Fig 3: FPGA acceleration scalability. Top: Total execution time for

Fig 4: Verilog code snippet for correlation computation on the FPGA.

Limitations

• Results are based solely on simulations using ideal Qiskit AerSimulator without a noise model; real NISQ hardware will have lower CHSH violation values due to noise.
• Current FPGA prototype limited by UART communication overhead (~554 ms per iteration) rather than hardware computation speed; optimized USB 3.0 interface is projected but not yet demonstrated.
• LLM optimization improves quality but does not reduce iterations compared to simpler fallback local perturbation; actual acceleration of convergence remains modest in these experiments.
• No adversarial robustness testing or security evaluation against malicious actors attempting to spoof certification results.
• Evaluation limited to CHSH inequality for bipartite entanglement certification; scalability to larger quantum systems and more complex certification protocols not demonstrated.
• Assumes availability and reliability of pretrained open-source LLMs with continuous online access for optimization, which may introduce latency and external dependency in real deployments.

Open questions / follow-ons

• How effective is the LLM-guided optimization on real, noisy NISQ hardware with fluctuating error rates and decoherence?
• Can the modular QSE architecture be extended to certify multipartite or higher-dimensional entanglement beyond CHSH scenarios?
• What trade-offs exist between FPGA acceleration, communication overhead, and overall system latency in deployed hardware-software integration?
• Could reinforcement learning models trained specifically on quantum hardware logs outperform general-purpose LLMs in parameter optimization?

Why it matters for bot defense

For bot-defense engineers and CAPTCHA practitioners, this work illustrates how hybrid classical-quantum software frameworks guided by systematic engineering principles can tackle certification challenges posed by noisy and unstable quantum computing hardware. Although the focus is on entanglement certification, the demonstrated use of FPGAs for accelerating classical computations and AI models for adaptive parameter tuning highlights best practices in integrating heterogeneous technologies under modular, reproducible architectures. CAPTCHA systems requiring robust bot detection might draw analogies from such adaptive optimization approaches to continuously tune challenge parameters based on real-time observations, leveraging AI guidance and hardware acceleration for latency-sensitive workflows. However, quantum certification pertains more directly to correctness guarantees of emerging quantum infrastructures than to classical bot detection per se.

Cite

@article{arxiv2607_07597,
  title={ Quantum Software Engineering in Practice: FPGA and AI Integration for Quantum Certification },
  author={ Marcos Guillermo Lammers and José Manuel Suárez and Adrián Pousa and Luis Mariano Bibbó and Alejandro Fernández },
  journal={arXiv preprint arXiv:2607.07597},
  year={ 2026 },
  url={https://arxiv.org/abs/2607.07597}
}

Read the full paper

• arXiv:2607.07597 (abstract)
• arXiv:2607.07597 (PDF)