ReSCom: A Reconfigurable Spiking Neural Network Accelerator Using Stochastic Computing
Source: arXiv:2606.13560 · Published 2026-06-11 · By Ali Alipour Fereidani, Mohammad Rasoul Roshanshah, Saeed Safari
TL;DR
This paper presents ReSCom, a reconfigurable hardware accelerator for Spiking Neural Networks (SNNs) that combines stochastic computing with exact fixed-point arithmetic to achieve energy-efficient and numerically stable inference. The core innovation is selectively applying stochastic computing to the multiplication operations within neuron dynamics—where hardware complexity and power consumption are highest—while maintaining deterministic fixed-point addition and subtraction to avoid error accumulation in recurrent neuron state updates. This hybrid approach enables runtime trade-offs between accuracy, latency, and energy by tuning the length of stochastic bit-streams.
The architecture unifies multiple neuron models (Integrate-and-Fire, Leaky Integrate-and-Fire, and Synaptic) within a single reconfigurable neuron core, allowing dynamic adaptation for diverse accuracy and biological realism requirements. Experimental evaluation on MNIST classification implemented on a Xilinx Artix-7 FPGA demonstrates competitive 92.80% accuracy with an operational energy consumption of approximately 0.05 mJ per inference at 100 MHz. Compared to DSP-based multipliers and other multiplier implementations, the ReSCom design achieves over 70% power reduction, with moderate hardware resource usage and stable operating frequency. The study also characterizes accuracy versus energy trade-offs across stochastic bit-stream lengths, showing that longer bitstreams reduce stochastic approximation error but at an energy cost, with the Synaptic neuron model being most sensitive to these trade-offs.
Key findings
- ReSCom achieves 92.80% MNIST classification accuracy on FPGA with only 0.05 mJ energy per image at 100 MHz.
- Stochastic multiplier reduces power consumption by over 70% compared to DSP-based multiplier while maintaining similar operating frequency (~130 MHz vs 129 MHz).
- Complete FPGA implementation occupies 57.84% of LUTs and 16.44% BRAM of the Xilinx Artix-7 device.
- Hardware accuracy gap vs software baseline: IF neuron 96.82% vs 97.06%, LIF neuron 92.80% vs 97.71%, Synaptic neuron 89.85% vs 97.49%.
- Increasing stochastic bit-stream length reduces accuracy drop but increases energy consumption; Synaptic neurons exhibit the largest error sensitivity.
- Stochastic multiplication produces error distributions tightly centered around zero, unlike stochastic addition and subtraction which yield larger and more variable errors.
- Time-multiplexed fully connected layer computation allows reuse of hardware multipliers and reduces logic use.
- Reconfigurable neuron design supports runtime switching among IF, LIF, and Synaptic models via a simple control signal.
Threat model
n/a — The paper addresses hardware design challenges rather than security threats; no adversary capabilities or threat scenarios are defined.
Methodology — deep read
Threat Model & Assumptions: The adversary context is implicit—this is not a security-focused paper. Instead, the design assumes noisy/stochastic arithmetic can destabilize recurrent neuron updates, so numerical stability is critical. The design must manage approximation error to ensure inference accuracy equivalent to software baselines.
Data: The MNIST dataset serves as the evaluation benchmark. Input images are downsampled from 28x28 to 16x16 pixel grayscale images (256 features). Each pixel is normalized to [0,1] and then converted to spike trains with stochastic encoding using Bernoulli, Normal, or Poisson distributions. The network comprises one hidden fully connected layer of 256 neurons and an output layer of 10 neurons. Training is performed offline with the snnTorch framework for 10 epochs.
Architecture & Algorithm: ReSCom contains three components: input interface for spike encoding; network computation unit (time-multiplexed FC layers); output interface for spike counting classification. The core innovation is a hybrid arithmetic scheme where stochastic computing is applied only to neuronal multiplication operations (via LFSR-generated bitstreams and bitwise AND gates), while accumulation steps use exact fixed-point add/subtract to avoid error buildup. The neuron core is reconfigurable among IF, LIF, and Synaptic models, controlled by a 2-bit mode input selecting operations such as thresholding, leakage, and synaptic state updates. Weights are stored in FPGA block RAM.
Training regime: The underlying SNN model is trained in software (snnTorch) with batch size 128, learning rate 1e-3, over 10 epochs with preset neuron parameters (threshold, leak factors). Bitstream length for stochastic multiplier is a key hyperparameter explored from 16 to 1024 bits.
Evaluation protocol: Metrics include classification accuracy on MNIST test set with hardware vs software comparison, power consumption measured on FPGA with different multiplier implementations (stochastic, DSP, array, shift-add), LUT and BRAM resource utilization, maximum clock frequency, and energy per image. Accuracy-energy trade-offs are evaluated while varying bit-stream precision. Baselines include previous FPGA SNN implementations under same conditions. No adversarial or distribution shift tests.
Reproducibility: The paper does not explicitly mention code or hardware release. The dataset (MNIST) and training framework (snnTorch) are public. Hardware implementation details including FPGA platform (Xilinx Artix-7) and resource usage are fully documented.
Concrete Example: For MNIST inference, a 16x16 normalized image is preprocessed in software then encoded to spike trains via stochastic encoding. These spike streams feed into the FPGA architecture where the hybrid stochastic multiplier multiplies spikes with weights stored in BRAM. Neuron membrane potentials are updated using exact accumulation plus stochastic multiplication per time step. After 10 time steps, output spikes are counted, and the neuron with highest spike count is predicted. Hardware power is measured and results correlate with software simulation accuracy, validating the architecture.
Technical innovations
- Selective use of stochastic computing exclusively for multiplication operations in neuron dynamics to reduce hardware complexity while maintaining numerical stability.
- Unified, reconfigurable neuron microarchitecture supporting IF, LIF, and Synaptic neuron models within a single hardware instance configurable at runtime.
- Dynamic accuracy–latency–energy trade-off tuning enabled by adjustable stochastic bit-stream length controlling precision of multiplication.
- Time-multiplexed fully connected layer computation allowing a shared multiplier module to serve multiple neurons, optimizing hardware resource utilization.
Datasets
- MNIST — 70,000 handwritten digit images (60,000 train, 10,000 test) — public dataset
Baselines vs proposed
- DSP-based multiplier: power = 132.42 mW vs proposed stochastic multiplier: 77 mW
- Array multiplier: LUT usage = 411,007 vs stochastic multiplier: 77,848 LUTs
- Shift-Add multiplier: LUT usage = 305,437 vs stochastic multiplier: 77,848 LUTs
- ReSCom energy per inference: 0.05 mJ vs prior SNN FPGA implementations ranging from 0.80 mJ to 13 mJ
- Hardware accuracy (LIF model): 92.80% vs software baseline: 97.71%
Limitations
- Hardware inference accuracy degrades compared to software baseline, especially for LIF and Synaptic neurons, due to stochastic approximation noise.
- Latency increases due to bit-stream generation for stochastic multiplier limiting throughput despite energy savings.
- Evaluation limited to MNIST dataset and fully-connected networks; lacks tests on more complex datasets or network architectures.
- No adversarial robustness or distribution shift evaluations conducted.
- No online learning or adaptive parameter tuning implemented; fixed offline training.
- Reproducibility limited by absence of public hardware source code or FPGA bitstreams.
Open questions / follow-ons
- How would the proposed hybrid stochastic computing approach scale to convolutional or recurrent SNN architectures and larger datasets?
- What is the impact of stochastic computing noise on online learning algorithms such as spike-timing-dependent plasticity implemented in hardware?
- Can further optimization reduce the latency overhead introduced by stochastic bit-stream generation while preserving energy efficiency?
- What are the robustness properties of ReSCom accelerators under hardware faults or process variation affecting stochastic computations?
Why it matters for bot defense
Bot-defense practitioners designing low-power, real-time CAPTCHA analysis or bot-detection accelerators could consider hybrid stochastic computing to reduce hardware multiplier complexity while balancing power and accuracy. The ability to reconfigure neuron models dynamically and tune stochastic precision at runtime offers flexibility to optimize for latency-energy trade-offs critical in embedded security devices. However, stochastic approximation noise and latency penalties must be carefully managed, especially for applications requiring stable and high-accuracy inference under adversarial conditions. This research highlights the potential to reduce resource overhead in spiking neural computations, a paradigm increasingly explored for efficient, event-driven bot detection mechanisms. Furthermore, stochastic computing’s robustness to transient errors could be advantageous in noisy environments typical of real-world bot-defense deployments.
Cite
@article{arxiv2606_13560,
title={ ReSCom: A Reconfigurable Spiking Neural Network Accelerator Using Stochastic Computing },
author={ Ali Alipour Fereidani and Mohammad Rasoul Roshanshah and Saeed Safari },
journal={arXiv preprint arXiv:2606.13560},
year={ 2026 },
url={https://arxiv.org/abs/2606.13560}
}