Practical gates by Majorana fermion motion
Source: arXiv:2606.03916 · Published 2026-06-02 · By Yuri D. Lensky, Bryce Kobrin, Kostyantyn Kechedzhi, Igor Aleiner
TL;DR
This paper addresses the challenging problem of implementing efficient, fault-tolerant logical gates on topological quantum error correcting codes, specifically planar 2D Pauli stabilizer codes, by describing logical degrees of freedom in terms of emergent point-like Majorana fermions. The key insight is that information is stored non-locally in pairwise fermion parities of spatially separated Majoranas, and that logical operations can be realized as braiding (motion) and fusion of these anyons. The authors develop a microscopic, lattice-precise theory of these Majorana fermions, capturing all length scales from lattice constants to large distance asymptotics, enabling a precise characterization and optimization of logical gate protocols. By exploiting this fine-grained locality and the ability to densely pack Majoranas in spacetime, they design braiding-based logical gates that reduce the space overhead compared to conventional lattice surgery while maintaining or improving logical error rates for near-term devices with realistic error models. Specifically, they construct explicit 2-qubit Clifford gates using fault-tolerant Majorana motion, and demonstrate via numerical benchmarking on the SI1000 noise model that their approach outperforms lattice surgery for a range of parameters. The work pioneers a fault-tolerant computational primitive based on compact Majorana motion, offering a promising new route to low overhead quantum error correction and gate synthesis compatible with existing surface-code hardware and decoders.
Key findings
- Encoding nσ undimerized Majorana fermions in disk topology allows max nσ/2 - 1 logical qubits.
- Code distance is bounded by the minimum of Wilson line length ℓW and ’t Hooft line length ℓH in the Majorana lattice graph.
- Dense Majorana packing (e.g., 3 qubits vs 2 qubits with same code distance) improves encoding rate by 50%.
- Fault-tolerant 2-qubit Clifford braiding gates can be implemented using paths preserving code distance d with time ∝ d/vσ.
- Braiding logical gates require 4d² + O(d) physical qubits vs lattice surgery’s 6d² + O(d), a ~33% reduction in overhead.
- Numerical benchmarks on the SI1000 error model show braiding outperforms lattice surgery in logical error rate at near-term error rates.
- Proper circuit design avoiding 2-qubit gate aligned Wilson lines prevents halving of effective code distance due to correlated errors.
- Measurement and initialization implemented via pair creation and annihilation of Majoranas, integrated into motion protocols.
Threat model
The adversary corresponds to local physical errors (Pauli errors) occurring randomly and independently according to a physical device noise model (such as SI1000), without strategic adversarial intervention. The noise model limits errors to low-weight stabilizer perturbations and does not include adaptive attacks, leakage, or correlated noise. The protocol assumes the ability to perform fault-tolerant stabilizer measurements and local gates according to the device connectivity constraints.
Methodology — deep read
The authors begin by defining a threat model consistent with quantum error correction: the adversary is local noise causing Pauli errors constrained by the physical device error model; they assume fault-tolerant stabilizer measurement and local gates but no adversarial adaptive attacks. They leverage prior work embedding n physical qubits into 4n Majorana fermions per qubit with parity gauge constraints, focusing on the undimerized Majoranas (nσ ≪ n) as logical degrees of freedom. Information is stored in fusion outcomes of Majorana pairs, with logical operators represented as Wilson lines (Pauli strings) connecting them; code distance is computed as the minimal weight among these logical operators and ’t Hooft loops separating particles. The dataset includes configurations derived from standard surface code lattices and variants with defects introduced for denser packing; logical qubit number and distances are computed via graph metrics (Manhattan distances on lattice and dual lattice).
They develop a microscopic Majorana graph model describing Pauli operators as bilinears of Majoranas, subject to gauge constraints fixing local fermion parities, allowing exact computation of code distances down to the lattice constant. Logical qubits correspond to parity sectors of even numbers of undimerized Majoranas. Syndromes correspond to fluxes of a Z(S)2 gauge field measured by stabilizer loops. They describe explicit circuits for moving Majoranas fault-tolerantly: either via isentropic gauge-invariant swaps generated by Wilson lines (unitary swaps on pairs of Majoranas) or via virtual particle motion implemented through sequences of pair creation and annihilation along paths with measurement of fusion outcomes. The latter requires repeated stabilizer measurements to maintain code distance due to measurement noise.
Stabilizer extraction circuits are designed for weights larger than 4 (due to dense Majorana packing) on devices with square grid connectivity and limited qubit readout. Careful circuit design avoids error patterns that halve effective code distance by preventing correlated 2-qubit errors aligned with Wilson lines. They construct explicit circuits for braiding-based 2-qubit Clifford gates preserving code distance d, requiring 4d² + O(d) qubits compared to 6d² + O(d) for lattice surgery.
Evaluation protocols include exact distance calculations via graph shortest path algorithms and numerical simulations benchmarking logical error rates on the SI1000 error model, a realistic noise model based on superconducting hardware. They compare fidelities of braiding protocols vs lattice surgery, showing better performance across parameter ranges. Abstractions include continuous metrics for quasi-static distances and circuit-level distance accounting for timing and parallelization. No closed code repository is mentioned, but circuit construction details and error model parameters are provided.
A concrete example: implementing a distance d=3 2-qubit Clifford gate by specifying Majorana positions and their braiding paths (Fig. 2), designing fault-tolerant syndrome extraction circuits interleaved with motion steps, and simulating logical error rates under SI1000 noise to demonstrate improved fidelity over lattice surgery with 50% fewer qubits. The entire pipeline integrates topological code theory, microscopic Majorana embedding, circuit synthesis, and numerical error modeling.
Technical innovations
- Microscopic lattice-precise Majorana fermion embedding of planar 2D Pauli codes unifying asymptotic and finite-scale properties.
- Novel code distance metrics combining Wilson and ’t Hooft line lengths computed exactly on Majorana graphs at lattice scale.
- Compact, distance-preserving braiding protocols for full 2-qubit Clifford gates exploiting dense Majorana packing.
- Explicit construction of fault-tolerant Majorana motion circuits using gauge-invariant swaps and virtual particle motion primitives.
- Mitigation of correlated 2-qubit gate errors by stabilizer measurement schedule and circuit design to preserve code distance.
Datasets
- SI1000 error model — realistic superconducting device noise model — public
Baselines vs proposed
- Lattice surgery: logical error rate = baseline; Braiding protocol logical error rate: up to 2× improvement at fixed qubit count
- Lattice surgery qubit overhead: 6d² + O(d); Braiding overhead: 4d² + O(d), ~33% reduction
Figures from the paper
Figures are reproduced from the source paper for academic discussion. Original copyright: the paper authors. See arXiv:2606.03916.
Fig 10: Left: qubit layout for lattice surgery. Right: qubit layout and Majorana fermion trajectories for braiding.
Fig 11: Stabilizer configurations of an unoptimized virtual particle-based braid, following steps 1-5 of Fig. 2. Time order is
Fig 12: The gate fidelity (or LER) for a simple virtual particle-based braiding gate (square points) as a function of the
Fig 8: Example stabilizer measurement circuits for Ma-
Fig 9: Fermion error analysis.
Fig 6 (page 9).
Limitations
- Analysis restricted to Pauli error models, no adversarial or non-Markovian noise considered.
- Reproducibility limited by absence of public code repository or open-source circuit implementations.
- Numerical benchmarks performed only for 2-qubit Clifford gates; scalability to larger codes and gates not demonstrated.
- Impact of device-specific constraints (connectivity, gate speeds) on optimal braiding speed vσ left for future work.
- Error models do not include correlated leakage or crosstalk errors present in some hardware.
- Theoretical proof of code distance preservation under their circuits deferred to future work; only heuristic and numerical evidence provided.
Open questions / follow-ons
- How to generalize fault-tolerant braiding protocols to multi-qubit gates beyond two logical qubits while maintaining or improving overhead?
- Detailed optimization of braiding speed vσ and parallelization on specific hardware architectures including crosstalk and timing constraints.
- Extension of the Majorana motion primitive to incorporate non-Clifford gates and universal logical gate sets.
- Analytical proof and circuit-level verification that the proposed stabilizer measurement and motion circuits exactly preserve code distance for all error models.
Why it matters for bot defense
Although primarily a quantum error correction and quantum computing paper, its methodology of interpreting logical operators as emergent Majorana fermions localized on lattices and using motion (braiding) primitives has conceptual parallels to designing and analyzing fault-tolerant transformations on encoded information. The principle of reducing overhead by exploiting microscopic degrees of freedom and their locality could inspire more efficient CAPTCHA or bot-defense scheme designs that consider complex state encodings and error models. Practitioners might consider analogues of logical braiding and fusion in challenge-response protocols to increase complexity while controlling resource cost. However, direct application is limited by the quantum-specific nature of Majorana codes and fault-tolerant gate synthesis.
Cite
@article{arxiv2606_03916,
title={ Practical gates by Majorana fermion motion },
author={ Yuri D. Lensky and Bryce Kobrin and Kostyantyn Kechedzhi and Igor Aleiner },
journal={arXiv preprint arXiv:2606.03916},
year={ 2026 },
url={https://arxiv.org/abs/2606.03916}
}